Method and System for Scalable Reduction in Registers With Sat-Based Resubstitution

ABSTRACT

A method, system, and computer program product for reducing the size of a logic network design, prior to verification of the logic network design. The method includes eliminating registers to reduce the size of the logic network design; thereby, increasing the speed and functionality of the verification process, and decreasing the size of the logic network design. The system identifies one or more compatible resubstitutions of a selected register, wherein the compatible resubstitution expresses the selected register as one or more pre-existing registers of fixed initial state. The resubstitutions are refined utilizing design invariants. When one more resubstitutions are preformed, the system eliminates the selected registers to reduce the size of the logic network design. As a result of the resubstitution process, a logic network design of reduced size is generated.

BACKGROUND

1. Technical Field

The present invention relates in general to logic network designs and inparticular to the scalable reduction of logic network designs.

2. Description of the Related Art

Within the field of logic synthesis there is a major endeavor tominimize the cost necessary to implement logic networks. Many algorithmsexist that are able to minimize the number of gates in the network. Oneexample of theses algorithms is resubstitution. Resubstitution is analgorithm that is utilized to re-express functions in a logic designnetwork in terms of other pre-existing functions. For example, withinthe Boolean functions F, G, and H, F may be expressed as F=func(G,H) forsome function (func). The total cost to implement the network may bereduced as the gates implementing G and H can be repurposed toadditionally implement F.

Traditionally resubstitution is performed using Binary Decision Diagrams(BDDs). However, BDDs do not scale well to industrial-sized logicnetworks, and therefore BDDs can only be used on very small logicnetworks. Resubstitution may also be performed utilizing a BooleanSatisfiability (SAT) solver. Incorporating a Boolean SAT solver scalesmuch better than the use of BDDs, thereby suggesting that resubstitutionmay be able to scale to industrial-sized logic networks.

Formal verification is utilized to prove and/or disprove the propertiesof a logic network design. In the field of formal verification, orformal model checking, there exist several algorithms to prove temporalproperties. Many of the algorithms utilized to prove temporal propertiesare not cost effective, and the computational complexity of thealgorithms is proportional to the size of the logic network design, onwhich the algorithm operates.

SUMMARY OF ILLUSTRATIVE EMBODIMENTS

Disclosed are a method, system, and computer program product forreducing the size of a logic network design, prior to verification ofthe logic network design. The method includes eliminating registers toreduce the size of the logic network design; thereby, increasing thespeed and functionality of the verification process, and decreasing thesize of the logic network design. The system identifies one or morecompatible resubstitutions of a selected register, wherein thecompatible resubstitution expresses the selected register as one or morepre-existing registers of fixed initial state. The resubstitutions arerefined utilizing design invariants. When one more resubstitutions arepreformed, the system eliminates the selected registers to reduce thesize of the logic network design. As a result of the resubstitutionprocess, a logic network design of reduced size is generated.

The above as well as additional objectives, features, and advantages ofthe present invention will become apparent in the following detailedwritten description.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention itself, as well as advantages thereof, will best beunderstood by reference to the following detailed description of anillustrative embodiment when read in conjunction with the accompanyingdrawings, wherein:

FIG. 1 provides a block diagram representation of an example dataprocessing system within which the invention is practiced, according toone embodiment of the invention;

FIG. 2 is a flow chart illustrating the method by which registers of alogic network design are eliminated, in accordance with one embodimentof the invention;

FIG. 3 is a flow chart illustrating the method by which invariantenhanced SAT-based resubstitution is performed, according to oneembodiment of the invention;

FIG. 4 is a flow chart illustrating the method by which one or moreinvariants are utilized to eliminate registers, in accordance with oneembodiment of the invention; and

FIG. 5 is a flow chart illustrating the method by which compatibleresubstitutions are analyzed, according to one embodiment of theinvention.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

Disclosed are a method, system, and computer program product forreducing the size of a logic network design, prior to verification ofthe logic network design. The method includes eliminating registers toreduce the size of the logic network design; thereby, increasing thespeed and functionality of the verification process, and decreasing thesize of the logic network design. The system identifies one or morecompatible resubstitutions of a selected register, wherein thecompatible resubstitution expresses the selected register as one or morepre-existing registers of fixed initial state. The resubstitutions arerefined utilizing design invariants. When one more resubstitutions arepreformed, the system eliminates the selected registers to reduce thesize of the logic network design. As a result of the resubstitutionprocess, a logic network design of reduced size is generated.

In the following detailed description of exemplary embodiments of theinvention, specific exemplary embodiments in which the invention may bepracticed are described in sufficient detail to enable those skilled inthe art to practice the invention, and it is to be understood that otherembodiments may be utilized and that logical, architectural,programmatic, mechanical, electrical and other changes may be madewithout departing from the spirit or scope of the present invention. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined by theappended claims and equivalents thereof.

Within the descriptions of the figures, similar elements are providedsimilar names and reference numerals as those of the previous figure(s).Where a later figure utilizes the element in a different context or withdifferent functionality, the element is provided a different leadingnumeral representative of the figure number. The specific numeralsassigned to the elements are provided solely to aid in the descriptionand not meant to imply any limitations (structural or functional orotherwise) on the described embodiment.

It is understood that the use of specific component, device and/orparameter names (such as those of the executing utility/logic describedherein) are for example only and not meant to imply any limitations onthe invention. The invention may thus be implemented with differentnomenclature/terminology utilized to describe thecomponents/devices/parameters herein, without limitation. Each termutilized herein is to be given its broadest interpretation given thecontext in which that terms is utilized.

With reference now to the figures, and in particular with reference toFIG. 1, a block diagram of a data processing system, in accordance withan embodiment of the present invention, is depicted. Data processingsystem 100 contains a processing storage unit (e.g., RAM 102) andprocessor 104. Data processing system 100 also includes non-volatilestorage 106 such as a hard disk drive or other direct-access storagedevice. An Input/Output (I/O) controller 108 provides connectivity tonetwork 110 through a wired or wireless link, such as network cable 112.I/O controller 108 also connects to user I/O devices 114 such as akeyboard, a display device, a mouse, or a printer through wired orwireless link 116, such as cables or a radio-frequency connection.System interconnect 118 connects processor 104, RAM 102, storage 106,and I/O controller 108.

Data processing system 100 stores several items of data and instructionswithin RAM 102, while operating in accordance with an embodiment of thepresent invention. These data instructions include initial logic network150 and output table 122 for interaction with verification environment124. Other data structures in RAM 102 include reduced logic network 140.Initial logic network 150 contains register(s) 160. Applications 128 andverification environment 124 interface with processor 104, RAM 102, I/Ocontroller 108, and storage 106 through operating system 130.Verification environment 124 includes satisfiability basedresubstitution (SBR) utility 145, and resubstitution components 175.Within resubstitution components 175 are basis set 136, and pre-existingregister 142. Additional components of data processing system 100 may beadded to or substituted for those shown without departing from the scopeof the present invention.

For simplicity of the description, the collective body of code thatenables various features of the system, including reducing the size of alogic network prior to verification of the logic network, is referred toherein as SBR utility 145. Among the software code/instructions/logicprovided by SBR utility 145, and which are specific to the invention,are: (a) code for enabling a Boolean function resubstitution, whereinthe Boolean function resubstitution expresses a register as one or morepre-existing registers; (b) code for dynamically selecting a relevantregister of a Boolean function basis set; (c) code for identifying oneor more resubstitutions of the relevant register, wherein theresubstitutions are compatible resubstitutions that expresses theselected relevant register as one or more pre-existing registers offixed initial state; (d) code for eliminating one or more registerswithin the logic network design when the resubstitution is received; and(e) code for generating a reduced sized logic network utilizing the oneor more resubstitutions. According to the illustrative embodiment, whenprocessor 104 executes SBR utility 145, data processing system 100initiates a series of functional processes that enable the abovefunctional features as well as additional features, described herein.

Those of ordinary skill in the art will appreciate that the hardwarecomponents and basic configuration depicted in FIG. 1 may vary. Theillustrative components within DPS 100 are not intended to beexhaustive, but rather are representative to highlight essentialcomponents that are utilized to implement the present invention. Forexample, other devices/components may be used in addition to or in placeof the hardware depicted. The depicted example is not meant to implyarchitectural or other limitations with respect to the presentlydescribed embodiments and/or the general invention. The data processingsystem depicted in FIG. 1 may be, for example, an IBM eServer pSeriessystem, a product of International Business Machines Corporation inArmonk, N.Y., running the Advanced Interactive Executive (AIX) operatingsystem or LINUX operating system.

In one embodiment, initial logic network 150 provides an original logicnetwork, comprising Boolean functions and registers, prior toverification. Within this initial logic network 150 are registers 160.SBR utility 145 receives one or more logic networks, and register 160 isidentified. SBR utility 145 receives a Boolean function resubstitution,to replace register 160. The Boolean function resubstitution is computedand integrated into the logic network to replace register 160. When theBoolean function resubstitution is integrated, register 160 iseliminated from initial logic network 150, thereby reducing initiallogic network 150.

In one embodiment, the speed of resubstitution is significantlyincreased utilizing a dynamic basis set. Boolean function basis set 136comprises one or more pre-existing registers 142 of the Boolean functionresubstitution. For example, when expressing a register F as a functionin terms of registers G and H, registers G an H are referred to as thebasis set. SBR utility 145 dynamically determines one or more relevantregisters of Boolean function basis set 136. Relevant registers areregisters that logically contribute to a function of the Booleanfunction resubstitution without creating an illegal logic network thatcontains combinational cycles. The existence of one or more relevantregisters is dynamically confirmed.

In yet another embodiment, invariants are utilized to strengthen theformulation of a Boolean resubstitution. Invariants are properties thathold in every reachable state of the design. For example, in theresubstitution F=func(G, H), the resubstitution would typically bediscarded if the function were not true for every valuation of theregisters. Instead, the resubstitution function condition is modified toonly require equality whenever the invariants hold. One or moreinvariants are received, wherein the invariants characterize a set ofunreachable states of the logic network. One or more invariants areassigned to one or more Boolean functions within the logic network. Whenperforming Boolean SAT-Based Resubstitution, the Boolean SAT solver isconstrained to only explore state assignments that satisfy allinvariants. An “unsatisfiable” answer from the solver indicates that aresubstitution exists. Constraining the solver, and limiting thesolver's ability to find satisfying assignments, increases the number ofresubstitutions that are detected in one or more subsequent cycles.

Invariants of the system may be developed from an algorithm thatautomatically determines properties of the logic network. In oneembodiment, the properties include one or more of: determining when asignal is constant in all reachable states, determining that two signalsare equivalent in all reachable states, determining that a set of foursignals have a fixed logical relationship in all reachable states; anddetermining that a Boolean implication exists between two signals in allreachable states. The system determines whether a Boolean function iscompatible when one or more properties of the Boolean function aredetected. When a Boolean function is found to not be compatible, themodified Boolean function is replaced with the original Booleanfunction.

FIGS. 2-5 are flow charts illustrating various methods by which theabove processes of the illustrative embodiments are completed. Althoughthe methods illustrated in FIGS. 2-5 may be described with reference tocomponents shown in FIG. 1, it should be understood that this is merelyfor convenience and alternative components and/or configurations thereofcan be employed when implementing the various methods. Key portions ofthe methods may be completed by SBR utility 145 executing on processor104 within data processing system 100 (FIG. 1) and controlling specificoperations on data processing system 100, and the methods are thusdescribed from the perspective of both SBR utility 145 and DPS 100.

FIG. 2 illustrates a method for eliminating registers to reduce the sizeof a logic network. Verification is especially sensitive to the numberof registers from a logic network and/or logic network design.Resubstitution is utilized to directly eliminate registers; thereby,increasing the speed and functionality of the verification process, anddecreasing the size of the logic network. The process of FIG. 2 beginsat initiator block 200 and proceeds to block 202, at which a logicnetwork is received. At block 204, one or more basis sets areinitialized as empty. Target registers, or registers to be replacedutilizing resubstitution, are received at block 206. At block 208 adecision is made as to whether a function resubstitution exists. If afunction resubstitution does not exists, the process returns to block204 where the basis set is initialized as empty (in preparation toreceive another register). If a function resubstitution exists, theprocess continues to block 210. At block 210 the register isre-expressed as a function of one or more pre-existing registers. Theregister is replaced by the newly expressed function, or resubstitutionfunction, at block 212.

At block 214, the logical value produced by the resubstitution functionin the initial state is determined. At block 216 a decision is madewhether the logical value produced by the newly expressed function underthe initial state equals the initial value of the original register. Ifthe logical value of the resubstitution function does not equal theinitial value of the original register, a multiplexer is introduced thatwill correct the value of the resubstitution function at time 0, atblock 215. The process continues to block 218, where the originalregister is eliminated from the logical network. If the logical value ofthe resubstitution function equals the initial value of originalregister, the original register is eliminated at block 218. A new logicnetwork is generated, at block 220, containing the resubstitutionfunction. The process ends at block 222.

A process for performing resubstitution over the reduced basis set isdepicted in FIG. 3. The process of FIG. 3 begins at initiator block 300and proceeds to block 302, at which a logic network is received. Atblock 304, one or more basis sets are initialized as empty. At block 306a decision is made whether a resubstitution is detected over the firstbasis set, as indicated by a satisfying assignment. If a resubstitutionis detected, the resubstitution is performed over the first basis set atblock 308. The reduced size logic network is generated at block 310. Theprocess ends at block 318. If a resubstitution is not detected, asatisfiable response to the satisfiability problem is received at block312, wherein a satisfiable response is a result received by the BooleanSatisfiability solver when a resubstitution does not exists. At block314 a decision is made whether entries are detected from the first basisset that may block the assignment. If entries exists that may block theassignment the process continues to block 316. At block 316 one or moreregisters are added to the first basis set from the second basis set.The process returns to block 306. If an entry, that may block theassignment, does not exist the process ends at block 318.

FIG. 4 depicts a method for utilizing one or more invariants toeliminate registers. The process of FIG. 4 begins at initiator block 400and proceeds to block 402, at which a logic network is received. Atblock 404 the logic network is associated with one or more invariants.At block 405 a SAT solver is invoked to test for the existence of aresubstitution. The Boolean satisfiability problem is constrained toonly explore solutions that are consistent with the invariants, therebylimiting the space of legal assignments. A decision is made, at block406, whether a satisfying assignment is detected. If the satisfyingassignment is detected, the process continues to block 408, where asatisfying assignment is received, and resubstitution does not exist.The process ends at block 414. If a satisfying assignment is notdetected (or unsatisfiable assignment detected), the process continuesto block 410 where one or more substitutions are received and thereplace register is eliminated. A reduced size logic network isgenerated at block 412. The process ends at block 414.

A method for by FIG. 5. Resubstitution is characterized by the cost toimplement substitution of an original register verses the cost toimplement the resubstitution function. In the system, the cost isevaluated as the number of logic network elements required to computethe original register verses the number of logic elements needed toproduce the resubstitution function. The process of FIG. 5 begins atinitiator block 500 and proceeds to block 502. One or more substitutionsare received at block 502. At block 504 the list of resubstitutions aresorted in order of increasing cost, with the resubstitutions that aremost efficient, or the most able to reduce the size of the logicnetwork, appearing first in the list. The newest element, or firstelement, on the list is processed at block 506. A decision is made, atblock 508, whether a legal logic network, free of combinational cycles,is detected from the results of the current resubstitution, inconjunction with previously accepted resubstitutions. If a legal logicnetwork is not detected, due to the resubstitution, the resubstitutionis not a compatible resubstitution, thereby is rejected at block 510. Atblock 512 the resubstitution is removed from the resubstitution list,and the process returns to block 506. If a legal logic network isdetected following the resubstitution, the resubstitution is acompatible resubstitution; thereby the resubstitution is accepted atblock 514. At block 516 the resubstitution is added to the list of thepreviously accepted resubstitutions. The process ends at block 518.

In the flow charts above, one or more of the methods are embodied in acomputer readable storage medium containing computer readable code suchthat a series of steps are performed when the computer readable code isexecuted (by a processing unit) on a computing device. In someimplementations, certain processes of the methods are combined,performed simultaneously or in a different order, or perhaps omitted,without deviating from the spirit and scope of the invention. Thus,while the method processes are described and illustrated in a particularsequence, use of a specific sequence of processes is not meant to implyany limitations on the invention. Changes may be made with regards tothe sequence of processes without departing from the spirit or scope ofthe present invention. Use of a particular sequence is therefore, not tobe taken in a limiting sense, and the scope of the present inventionextends to the appended claims and equivalents thereof.

As will be appreciated by one skilled in the art, the present inventionmay be embodied as a method, system, and/or computer program product.Accordingly, the present invention may take the form of an entirelyhardware embodiment, an entirely software embodiment (includingfirmware, resident software, micro-code, etc.) or an embodimentcombining software and hardware aspects that may all generally bereferred to herein as a “circuit,” “module,” “logic”, or “system.”Furthermore, the present invention may take the form of a computerprogram product on a computer-usable storage medium havingcomputer-usable program code embodied in or on the medium.

As will be further appreciated, the processes in embodiments of thepresent invention may be implemented using any combination of software,firmware, microcode, or hardware. As a preparatory step to practicingthe invention in software, the programming code (whether software orfirmware) will typically be stored in one or more machine readablestorage mediums such as fixed (hard) drives, diskettes, magnetic disks,optical disks, magnetic tape, semiconductor memories such as RAMs, ROMs,PROMs, etc., thereby making an article of manufacture in accordance withthe invention. The article of manufacture containing the programmingcode is used by either executing the code directly from the storagedevice, by copying the code from the storage device into another storagedevice such as a hard disk, RAM, etc., or by transmitting the code forremote execution using transmission type media such as digital andanalog communication links. The medium may be electronic, magnetic,optical, electromagnetic, infrared, or semiconductor system (orapparatus or device) or a propagation medium. Further, the medium may beany apparatus that may contain, store, communicate, propagate, ortransport the program for use by or in connection with the executionsystem, apparatus, or device. The methods of the invention may bepracticed by combining one or more machine-readable storage devicescontaining the code according to the described embodiment(s) withappropriate processing hardware to execute the code contained therein.An apparatus for practicing the invention could be one or moreprocessing devices and storage systems containing or having networkaccess (via servers) to program(s) coded in accordance with theinvention. In general, the term computer, computer system, or dataprocessing system can be broadly defined to encompass any device havinga processor (or processing unit) which executes instructions/code from amemory medium.

Thus, it is important that while an illustrative embodiment of thepresent invention is described in the context of a fully functionalcomputer (server) system with installed (or executed) software, thoseskilled in the art will appreciate that the software aspects of anillustrative embodiment of the present invention are capable of beingdistributed as a program product in a variety of forms, and that anillustrative embodiment of the present invention applies equallyregardless of the particular type of media used to actually carry outthe distribution. By way of example, a non exclusive list of types ofmedia, includes recordable type (tangible) media such as floppy disks,thumb drives, hard disk drives, CD ROMs, DVDs, and transmission typemedia such as digital and analogue communication links.

While the invention has been described with reference to exemplaryembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted forelements thereof without departing from the scope of the invention. Inaddition, many modifications may be made to adapt a particular system,device or component thereof to the teachings of the invention withoutdeparting from the essential scope thereof. Therefore, it is intendedthat the invention not be limited to the particular embodimentsdisclosed for carrying out this invention, but that the invention willinclude all embodiments falling within the scope of the appended claims.Moreover, the use of the terms first, second, etc. do not denote anyorder or importance, but rather the terms first, second, etc. are usedto distinguish one element from another.

1. A method for reducing the size of a logic network design, prior toverification of the logic network design, utilizing a resubstitution,wherein the resubstitution is a Boolean function resubstitution, saidmethod comprising: dynamically selecting a relevant register of aBoolean function basis set; identifying one or more resubstitutions ofthe relevant register, wherein the resubstitutions are compatibleresubstitutions that expresses the selected relevant register as one ormore pre-existing registers of fixed initial state; refining theresubstitution utilizing design invariants; and generating a logicnetwork design of reduced size utilizing the one or moreresubstitutions.
 2. The method of claim 1, further comprising: receivingone or more logic network designs; identifying a register within thelogic network design; determining one or more pre-existing registers,with a fixed initial state, to replace the register of the logic networkdesign; computing the resubstitution, wherein the resubstitutionreplaces the register; and eliminating one or more registers within thelogic network design when the resubstitution is received.
 3. The methodof claim 1, further comprising; when the Boolean function basis set isthe one or more pre-existing registers of the resubstitution,dynamically determining one or more relevant registers within theBoolean function basis set; and dynamically confirming the existence ofone or more relevant registers, wherein a relevant register logicallycontributes to a function of the resubstitution.
 4. The method of claim1, further comprising: receiving one or more invariants, wherein theinvariants store information about one or more reachable states of thelogic network design; detecting the invariants when the invariants arelocal properties of the logic network design, wherein the localproperties are one or more of: a signal is constant in all reachablestates; two signals are equivalent in all reachable states; a set offour signals have a fixed logical relationship in all reachable states;and a Boolean implication exists between two signals in all reachablestates; assigning one or more invariants to one or more Booleanfunctions; and enabling one or more resubstitutions to be detected whena Boolean Satisfiability (SAT) formulation contains the one or moreinvariants.
 5. The method of claim 4, further comprising: receiving oneor more of a satisfiable and unsatisfiable result from a Boolean SATsolver, wherein when a satisfiable result is received and theresubstitution does not exist, assigning one or more additional signalsto the Boolean function basis set, wherein assigning one or moreadditional signals to the Boolean function basis set increases aprobability that the resubstitution is detected in one or moresubsequent cycles.
 6. The method of claim 1, further comprising:detecting a resubstitution when the resubstitution is a compatibleresubstitution, wherein a compatible resubstitution enables the logicnetwork design to operate free of combinational cycles when thecompatible resubstitution and one or more previously acceptedresubstitutions operate simultaneously in the logic network design. 7.The method of claim 2, further comprising: dynamically eliminating oneor more registers of the Boolean function basis set when the one or moreregisters do not logically contribute to the function of theresubstitution.
 8. The method of claim 1, further comprising:determining when the resubstitution is a beneficial resubstitution,wherein one or more resubstitutions are characterized by one or more of:cost and efficacy; generating a list of resubstitutions, wherein theresubstitutions are listed in order of one of: highest to lowest costand highest to lowest efficacy, and lowest to highest cost and lowest tohighest efficacy; selecting a first resubstitution; invoking theresubstitution process; detecting when the resubstitution enables alegal logic network design, wherein the resubstitution is operating withone or more previously accepted resubstitutions; and when aresubstitution enables an illegal logic network design, eliminating theresubstitution from the list of resubstitutions.
 9. The method of claim3, further comprising: enabling one or more relevant registers to beadded to a first Boolean function basis set from a second Booleanfunction basis set, when a satisfying assignment is detected;determining when a satisfying assignment is blocked, wherein when thesatisfying assignment is blocked a Boolean satisfiability problem ispartitioned into a series of smaller problems; invoking an incrementalBoolean SAT solver; detecting a solution to the one or more partitionedproblems; determining one or more resubstitutions when the solution isreceived; and generating a reduced size logic network design.
 10. Acomputer system for reducing the size of a logic network design, priorto verification of the logic network design, utilizing a resubstitution,wherein the resubstitution is a Boolean function resubstitution, saidcomputer system comprising: a processor component; and a utilityexecuting on the processor component and which comprises code thatenables completion of the following functions: means for dynamicallyselecting a relevant register of a Boolean function basis set; means foridentifying one or more resubstitutions of the relevant register,wherein the resubstitutions are compatible resubstitutions thatexpresses the selected relevant register as one or more pre-existingregisters of fixed initial state; means for refining the resubstitutionutilizing design invariants; and means for generating a logic networkdesign of reduced size utilizing the one or more resubstitutions. 11.The computer system of claim 10, further comprising: means for receivingone or more logic network designs; means for identifying a registerwithin the logic network design; means for determining one or morepre-existing registers, with a fixed initial state, to replace theregister of the logic network design; means for computing theresubstitution, wherein the resubstitution replaces the register; meansfor eliminating one or more registers within the logic network designwhen the resubstitution is received; and means for receiving one or moreof a satisfiable and unsatisfiable result from a Boolean SAT solver,wherein when a satisfiable result is received and the resubstitutiondoes not exist, assigning one or more additional signals to the Booleanfunction basis set, wherein assigning one or more additional signals tothe Boolean function basis set increases a probability that theresubstitution is detected in one or more subsequent cycles.
 12. Thecomputer system of claim 10, further comprising; when the Booleanfunction basis set is the one or more pre-existing registers of theresubstitution, means for dynamically determining one or more relevantregisters within the Boolean function basis set; and means fordynamically confirming the existence of one or more relevant registers,wherein a relevant register logically contributes to a function of theresubstitution.
 13. The computer system of claim 10, further comprising:means for receiving one or more invariants, wherein the invariants storeinformation about one or more reachable states of the logic networkdesign; means for detecting the invariants when the invariants are localproperties of the logic network design, wherein the local properties areone or more of: a signal is constant in all reachable states; twosignals are equivalent in all reachable states; a set of four signalshave a fixed logical relationship in all reachable states; and a Booleanimplication exists between two signals in all reachable states; meansfor assigning one or more invariants to one or more Boolean functions;and means for enabling one or more resubstitutions to be detected when aBoolean Satisfiability (SAT) formulation contains the one or moreinvariants.
 14. The computer system of claim 10, further comprises:means for detecting a resubstitution when the resubstitution is acompatible resubstitution, wherein a compatible resubstitution enablesthe logic network design to operate free of combinational cycles whenthe compatible resubstitution and one or more previously acceptedresubstitutions operate simultaneously in the logic network design;means for determining when the resubstitution is a beneficialresubstitution, wherein one or more resubstitutions are characterized byone or more of: cost and efficacy; means for generating a list ofresubstitutions, wherein the resubstitutions are listed in order of oneof: highest to lowest cost and highest to lowest efficacy, and lowest tohighest cost and lowest to highest efficacy; means for selecting a firstresubstitution; means for invoking the resubstitution process; means fordetecting when the resubstitution enables a legal logic network design,wherein the resubstitution is operating with one or more previouslyaccepted resubstitutions; and when a resubstitution enables an illegallogic network design, means for eliminating the resubstitution from thelist of resubstitutions.
 15. The computer system of claim 11, furthercomprising: means for dynamically eliminating one or more registers ofthe Boolean function basis set when the one or more registers do notlogically contribute to the function of the resubstitution; means forenabling one or more relevant registers to be added to a first Booleanfunction basis set from a second Boolean function basis set, when asatisfying assignment is detected; means for determining when asatisfying assignment is blocked, wherein when the satisfying assignmentis blocked a Boolean satisfiability problem is partitioned into a seriesof smaller problems; means for invoking an incremental Boolean SATsolver; means for detecting a solution to the one or more partitionedproblems; means for determining one or more resubstitutions when thesolution is received; and means for generating a reduced size logicnetwork design.
 16. A computer program product in a computer-readablestorage medium for reducing the size of a logic network design, prior toverification of the logic network design, utilizing a resubstitution,wherein the resubstitution is a Boolean function resubstitution, saidcomputer program product comprising: a computer-readable storage medium;and program code on the computer-readable storage medium that whenexecuted by a computer device provides the functions of: dynamicallyselecting a relevant register of a Boolean function basis set;identifying one or more resubstitutions of the relevant register,wherein the resubstitutions are compatible resubstitutions thatexpresses the selected relevant register as one or more pre-existingregisters of fixed initial state; refining the resubstitution utilizingdesign invariants; and generating a logic network design of reduced sizeutilizing the one or more resubstitutions.
 17. The computer programproduct of claim 16, further comprises program code for: receiving oneor more logic network designs; identifying a register within the logicnetwork design; determining one or more pre-existing registers, with afixed initial state, to replace the register of the logic networkdesign; computing the resubstitution, wherein the resubstitutionreplaces the register; eliminating one or more registers within thelogic network design when the resubstitution is received; receiving oneor more of a satisfiable and unsatisfiable result from a Boolean SATsolver, wherein when a satisfiable result is received and theresubstitution does not exist, assigning one or more additional signalsto the Boolean function basis set, wherein assigning one or moreadditional signals to the Boolean function basis set increases aprobability that the resubstitution is detected in one or moresubsequent cycles; when the Boolean function basis set is the one ormore pre-existing registers of the resubstitution, dynamicallydetermining one or more relevant registers within the Boolean functionbasis set; and dynamically confirming the existence of one or morerelevant registers, wherein a relevant register logically contributes toa function of the resubstitution.
 18. The computer program product ofclaim 16, further comprises program code for: receiving one or moreinvariants, wherein the invariants store information about one or morereachable states of the logic network design; detecting the invariantswhen the invariants are local properties of the logic network design,wherein the local properties are one or more of: a signal is constant inall reachable states; two signals are equivalent in all reachablestates; a set of four signals have a fixed logical relationship in allreachable states; and a Boolean implication exists between two signalsin all reachable states; assigning one or more invariants to one or moreBoolean functions; and enabling one or more resubstitutions to bedetected when a Boolean Satisfiability (SAT) formulation contains theone or more invariants.
 19. The computer program product of claim 16,further comprises program code for: detecting a resubstitution when theresubstitution is a compatible resubstitution, wherein a compatibleresubstitution enables the logic network design to operate free ofcombinational cycles when the compatible resubstitution and one or morepreviously accepted resubstitutions operate simultaneously in the logicnetwork design; determining when the resubstitution is a beneficialresubstitution, wherein one or more resubstitutions are characterized byone or more of: cost and efficacy; generating a list of resubstitutions,wherein the resubstitutions are listed in order of one of: highest tolowest cost and highest to lowest efficacy, and lowest to highest costand lowest to highest efficacy; selecting a first resubstitution;invoking the resubstitution process; detecting when the resubstitutionenables a legal logic network design, wherein the resubstitution isoperating with one or more previously accepted resubstitutions; and whena resubstitution enables an illegal logic network design, eliminatingthe resubstitution from the list of resubstitutions.
 20. The computerprogram product of claim 17, further comprises program code for:dynamically eliminating one or more registers of the Boolean functionbasis set when the one or more registers do not logically contribute tothe function of the resubstitution; enabling one or more relevantregisters to be added to a first Boolean function basis set from asecond Boolean function basis set, when a satisfying assignment isdetected; determining when a satisfying assignment is blocked, whereinwhen the satisfying assignment is blocked a Boolean satisfiabilityproblem is partitioned into a series of smaller problems; invoking anincremental Boolean SAT solver; detecting a solution to the one or morepartitioned problems; determining one or more resubstitutions when thesolution is received; and generating a reduced size logic networkdesign.